Resistance bi-stability in resonant tunneling diode pillar arrays

Resonant tunneling diodes ~RTDs! are one of the most promising quantum effect devices for practical applications. The presence of negative differential resistance at room temperature allows RTDs to be used as memory storage devices. Recent work has demonstrated that the buildup of electron charge in the well can have a strong influence on the bias required to switch between stable states. In addition, single electron charging effects become pronounced as the size of the device is reduced. For asymmetric barriers the tunneling characteristics of a quasi-one-dimensional RTD at low temperature can be completely dominated by electron charging. To study the influence of electron charging on small scale RTDs we have produced a new type of device consisting of an array of randomly sized RTD pillars. Each pillar is less than 50 nm in diameter so that the single electron charging energy for tunneling into the well is expected to approach kT at room temperature. When measured in parallel, the pillars show switching between a low and a high resistance state with a maximum room temperature peak to valley current ratio of 500:1. Both resistance states are stable with zero-bias on the device, suggesting that the device may be used for non-volatile memory storage. We fabricate our samples using a natural lithographic process. First, we evaporate a thin gold film onto the semiconductor surface. It is well documented that for film thicknesses less than around 10 nm, gold forms a granular layer composed of disconnected islands. The gold islands partially mask the underlying material so that plasma etching in a SiCl4/Ar environment selectively removes the material between the dots and produces an array of semiconductor pillars. Figure 1 shows an electron beam micrograph of a typical sample surface after etching. Here, an array of randomly shaped pillars 350 nm high and 20–50 nm in diameter is seen. Some of the pillars are partially connected to form larger structures. The pillar array uniformly covers the vast majority of a 535 mm sample surface. Our device is drawn schematically in Fig. 2. A RTD pillar array is formed by etching a double barrier AlAs/GaAs heterostructure in the manner described above. A top contact to the pillar array is made by evaporating a 30330 micron gold pad. The contact pad does not fill the gaps between the pillars because the grain size of the gold ~20–50 nm! is approximately the same as the pillar spacing. The back contact